1. Field of the Invention
The present invention relates to a solid-state image-sensing device having pixels outputting an electric signal representing incident light. More specifically, the invention relates to a solid-state image-sensing device of which each pixel is built with transistors.
2. Description of Related Art
Used in various applications, solid-state image-sensing devices are classified into a CCD type and a CMOS type depending on the means they use to read out (extract) the photoelectric charges generated in photoelectric conversion elements. In the CCD type, the photoelectric charges resulting from photoelectric conversion by photodiodes are accumulated in the photodiodes and, at the end of an integration period for which they are accumulated, the accumulated photoelectric charges are outputted all at once to CCDs serving as signal transfer paths. The photoelectric charges thus outputted to the signal transfer paths are sequentially fed to an output circuit by being transferred while being accumulated in potential wells in the signal transfer paths. Thus the photodiodes of the individual pixels perform integration with identical timing, and this mode of image sensing operation is called “global shutter mode”.
On the other hand, in the CMOS type, the electric charges accumulated in the pn-junction capacitances of photodiodes are read out directly via MOS transistors. Thus, in the CMOS type, signal electric charges attributable to the photoelectric charges resulting from photoelectric conversion by the photodiodes are transferred instantaneously via signal lines. Thus, while the pixels in a given horizontal row perform integration with identical timing, the pixels in different rows perform integration with different timing to achieve the shooting of one frame. This mode of operation is called “rolling shutter mode”.
Disadvantageously, both the CCD type and the CMOS type suffer from narrow dynamic ranges. As an improvement, there have conventionally been proposed CMOS-type solid-state image-sensing devices that perform logarithmic conversion by converting the amount of incident light logarithmically (see Japanese Patent No. 2836147). These solid-state image-sensing devices have dynamic ranges as wide as expressed by five- to six-digit figures. Thus, with these solid-state image-sensing devices, even when a subject whose brightness distribution spreads across a considerably wide range is sensed, all the brightness information within that brightness distribution can be outputted in a form converted into an electric signal.
Now, the principle of the operation of a solid-state image-sensing device performing logarithmic conversion will be described briefly. FIGS. 13A and 13B are each a circuit diagram showing the basic configuration of each pixel in a CMOS-type solid-state image-sensing device. According to one configuration of each pixel in a CMOS-type solid-state image-sensing device, as shown in FIG. 13A, there are provided: a photodiode PD that serves as a photosensitive element performing photoelectric conversion; an N-channel MOS transistor T1 that has its gate and drain connected to the anode of the photodiode PD and that operates in a sub-threshold region; an N-channel MOS transistor T2 that has its gate connected to the node between the drain of the MOS transistor T1 and the anode of the photodiode PD; and a capacitor C of which one end is connected to the source of the MOS transistor T2. Here, the output signal is derived from the node between the source of the MOS transistor T2 and the capacitor C.
According to another configuration, as shown in FIG. 13B, there are provided: a photodiode PD; a MOS transistor T12 that has its source connected to the cathode of the photodiode PD and that operates in a sub-threshold region; a P-channel MOS transistor T2a that has its gate connected to the node between the source of the MOS transistor T12 and the cathode of the photodiode PD; and a capacitor C of which one end is connected to the source of the MOS transistor T2a. Here, the output signal is derived from the node between the source of the MOS transistor T2a and the capacitor C.
In these configurations, when the MOS transistors operate in a sub-threshold region, its gate voltage Vg, source voltage Vs, and drain current Id have the relation given by formula (1) below. In formula (1), q represents the amount of electric charge of an electron, k represents the Boltzmann constant, n represents the sub-threshold constant dependent on the structure of the transistor, T represents the absolute temperature, Id0 represents the drain current Id at the moment that a sub-threshold current starts to flow, and Vt represents the threshold voltage.
                    Id        =                  Id          ⁢                                          ⁢          0          ×                      exp            ⁡                          [                                                q                  nkT                                ⁢                                  (                                      Vg                    -                    Vs                    -                    Vt                                    )                                            ]                                                          (        1        )            
In the configuration shown in FIG. 13A, when the operation of the MOS transistor T1 in the sub-threshold region causes the drain current Id given by formula (1) above to start to flow, the integrating circuit formed by the MOS transistor T2 and the capacitor C performs integration operation. Here, let the photoelectric current flowing through the photodiode PD be Ip and let the voltage appearing at the drain of the MOS transistor T1 be Vin, then, as a result of the MOS transistor T1 operating in the sub-threshold region, the relation given by formula (2) below holds.
                              I          p                =                  Id          ⁢                                          ⁢          0          ×                      exp            ⁡                          [                                                q                  nkT                                ⁢                                  (                                      Vin                    -                    Vt                                    )                                            ]                                                          (        2        )            
Assuming that the MOS transistor T2 has identical characteristics with MOS transistor T1, the MOS transistor T2 then operates, like the MOS transistor T1, in the sub-threshold region, and thus the drain current of the MOS transistor T2 flows through the capacitor C. Thus, let the capacitance of the capacitor C be C and the output voltage at the source of the MOS transistor T2 be Vout, then the relation given by formula (3) below holds.
                              C          ⁢                                    ⅆ              Nout                                      ⅆ              t                                      =                  Id          ⁢                                          ⁢          0          ×                      exp            ⁡                          [                                                q                  nkT                                ⁢                                  (                                      Vin                    -                    Vout                    -                    Vt                                    )                                            ]                                                          (        3        )            
The relations given by formulae (2) and (3) give the relation given by formula (4).
                                          exp            ⁡                          [                                                q                  nkT                                ⁢                Vout                            ]                                ⁢          dVout                =                              Ip            C                    ⁢          dt                                    (        4        )            
Assuming that, when the time t is 0, the output voltage Vout is 0, integrating formula (4) gives the output voltage Vout given by formula (5) below. That is, the output voltage Vout resulting from integration by the integrating circuit formed by the MOS transistor T2 and the capacitor C is proportional to the logarithm of the integral of the photoelectric current Ip. Thus, by finding the exponent of the output voltage Vout, it is possible to easily obtain a value proportional to the integral of the photoelectric current Ip.
                                                        Vout              =                            ⁢                                                nkT                  q                                ⁢                                  ln                  ⁡                                      [                                                                                            q                          nkTC                                                ⁢                                                  ∫                                                      Ip                            ⁢                                                          ⅆ                              t                                                                                                                          +                      1                                        ]                                                                                                                          ≈                            ⁢                                                nkT                  q                                ⁢                                  ln                  ⁡                                      [                                                                  q                        nkTC                                            ⁢                                              ∫                                                  Ip                          ⁢                                                      ⅆ                            t                                                                                                                ]                                                                                                          (        5        )            
In the configuration shown in FIG. 13B, a direct-current voltage Vr is fed, as a gate voltage, to the MOS transistor T12 to make it operate in the sub-threshold region. Here, assuming that the MOS transistors T12 and T2a have an equal sub-threshold constant n, which depends on their structure, let the constant depending on the relation between the characteristics of the MOS transistor T12 and the direct-current voltage Vr be “a”, then the output voltage Vout appearing at the source of the MOS transistor T2a is given by formula (6) below.
                    Vout        ≈                  Vr          -                                    nkT              q                        ⁢                          ln              ⁡                              [                                                      aq                    nkTC                                    ⁢                                      ∫                                          Ip                      ⁢                                              ⅆ                        t                                                                                            ]                                                                        (        6        )            
In a CMOS-type solid-state image-sensing device having pixels each configured basically as shown in FIG. 13A or 13B, since its shootable brightness range is wide compared with the brightness distribution of a subject, there appears, in a low-brightness or high-brightness region within the shootable brightness range, a region where no brightness data exists. To cope with this, the applicant of the present invention has proposed a CMOS-type solid-state image-sensing device that can be switched between linear conversion operation and logarithmic conversion operation as described above (Japanese Patent No. 3664035).
To automatize such switching between linear conversion operation and logarithmic conversion operation, the applicant has also proposed a CMOS-type solid-state image-sensing device in which the potential state of a transistor connected to a photodiode performing photoelectric conversion can be set appropriately (see JP-A-2002-300476). In this CMOS-type solid-state image-sensing device according to JP-A-2002-300476, by changing the potential state of the transistor, it is possible to switch the inflection point across which the device's photoelectric conversion is switched between linear conversion operation and logarithmic conversion operation.
A typical example of each pixel in solid-state image-sensing devices as exemplified by those disclosed in Japanese Patent No. 3664035 and JP-A-2002-300476 mentioned above is shown in FIG. 14. The pixel configuration shown in FIG. 14 is built on the basic configuration shown in FIG. 13A. Specifically, in the configuration shown in FIG. 14, the pixel that performs logarithmic conversion operation or that can be switched between linear conversion operation and logarithmic conversion operation includes, as in FIG. 13A, a photodiode PD, MOS transistors T1 and T2, and a capacitor C; in addition, it further includes: an N-channel MOS transistor T3 that receives at its gate the voltage appearing at the capacitor C to amplify it; an N-channel MOS transistor T4 that is connected between the source of the MOS transistor T3 and an output signal line 14 provided for the corresponding row; and an N-channel MOS transistor T5 for resetting the capacitor C.
In the pixel shown in FIG. 14 configured as described above, the MOS transistor T5, of which the drain is connected to the node between the capacitor C and the source of the MOS transistor T2, resets the voltage appearing at the gate of the MOS transistor T3. Moreover, as a result of linear conversion operation or logarithmic conversion operation, a voltage signal commensurate with the amount of incident light appears at the node between the capacitor C and the source of the MOS transistor T2, and this voltage signal is amplified by the MOS transistor T3. When the MOS transistor T4 is turned on, the voltage signal amplified by the MOS transistor T3 is outputted via the output signal line 14.
A CMOS-type solid-state image-sensing device of which each pixel is typically configured as shown in FIG. 14 performs vertical and horizontal scanning to perform image sensing operation in rolling shutter mode, and then outputs serially the image signals outputted from the individual pixels. In this way, image sensing operation is performed in rolling shutter mode, and thus image sensing operation in different rows is performed with different timing. As a result, in a case where a subject in a constantly changing state is sensed, or in a case where shooting is performed under flash light, image sensing cannot be performed under identical conditions in all pixels. This may eventually produce distortion in the sensed image.
To cope with this, the applicant has proposed solid-state image-sensing devices of which each pixel includes two capacitors to allow image sensing operation to be performed with identical timing in all pixels (see Japanese Patent No. 3493405 and JP-A-2004-349907). As an example of the configuration of these solid-state image-sensing devices, one that includes as the photoelectric conversion circuit the basic configuration shown in FIG. 13A is shown in FIG. 15.
The pixel shown in FIG. 15 includes, as in FIG. 14, a photodiode PD, MOS transistors T1 to T5, and a capacitor C; in addition, it further includes: a capacitor C1 that samples-and-holds the electric signal integrated by the capacitor C; an N-channel MOS transistor T100 that connects and disconnects the capacitors C and C1 to and from each other; and an N-channel MOS transistor T101 that serves as a switch for resetting the capacitor C1.
With the pixel shown in FIG. 15 configured as described above, the MOS transistor T1 to T5 and T100 operate with identical timing in all the pixels of a solid-state image-sensing device; thus the electric signals resulting from image sensing operation performed simultaneously are integrated in the capacitor C, and are then sampled-and-held in the capacitor C1. Then the MOS transistor T100 is turned off, and then horizontal and vertical scanning is performed so that image signals commensurate with the electric signals sampled-and-held in the capacitor C1 are amplified and outputted.
Specifically, immediately before the integration operation by the integrating circuit formed by the MOS transistor T2 and the capacitor C, in all pixels, the MOS transistor T5 is turned on so that the capacitor C is reset. Then the MOS transistor T5 is turned off so that a new integration period is started. Thereafter the MOS transistor T101 is turned on so that the capacitor C1 is reset, and then the MOS transistor T101 is turned off and also the MOS transistor T100 is turned on so that the voltage appearing at the capacitor C is sampled-and-held in the capacitor C1. When the MOS transistor T100 is then turned off, the integration operation in all pixels ends. In this way, image sensing operation in global shutter mode is achieved.
For the purpose of reducing dark current in solid-state image-sensing devices, there have been proposed solid-state image-sensing devices employing a buried diode (see JP-A-2006-050544). The solid-state image-sensing device disclosed in JP-A-2006-050544 includes, as shown in FIG. 16, a buried photodiode PDa that serves as a photoelectric conversion element; an N-channel MOS transistor T11 that has its source connected to the cathode of the buried photodiode PDa; an N-channel MOS transistor T12 that has its source connected to the drain of the MOS transistor T11; a MOS transistor T3 that has its gate connected to the node between the drain of the MOS transistor T11 and the source of the MOS transistor T12; and a MOS transistor T4 that has its drain connected to the source of the MOS transistor T3.
In the pixel configured as described above, as shown in FIG. 17, on a P-type substrate 30, a P-type well layer 31 is formed. In the surface of this P-type well layer 31, a P-type layer 20 is formed and an N-type buried layer 21 is buried; thus the buried photodiode PDa is formed. On the surface of a region contiguous with the region where the buried photodiode PDa is formed, a gate electrode 23 is formed with an insulating film 22 laid in between; thus a transfer gate TG is formed. In a region contiguous with the region where the transfer gate TG is formed, an N-type floating diffusion layer FD is formed. On the surface of a region contiguous with the region where the N-type floating diffusion layer FD is formed, a gate electrode 25 is formed with an insulating film 24 laid in between; thus a reset gate RG is formed. In a region contiguous with the region where the reset gate RG is formed, an N-type diffusion layer D is formed.
Here, the buried photodiode PDa has the highly-doped P-type layer 20 formed on the surface of the N-type buried layer 21. The N-type buried layer 21, the N-type floating diffusion layer FD, and the transfer gate TG together form the MOS transistor T1. The N-type floating diffusion layer FD, the N-type diffusion layer D, and the reset gate RG together form the MOS transistor T12. With the buried photodiode PDa formed in this way in the pixel, the potential at the surface of the P-type layer 20 is fixed at a potential equal to that at the channel stopper layer formed by the P-type layer around the buried photodiode PDa. The gate of the MOS transistor T3 is connected to the N-type floating diffusion layer FD.
By adopting the structure shown in FIG. 17 around the buried photodiode PDa, it is possible to suppress dark current occurring at the surface around the buried photodiode PDa, and it is thus possible to reduce dark current occurring in the pixel. In a signal output circuit provided in the stage following the pixel, correlative double sampling can be used, and thus it is also possible to eliminate kTC noise. On account of these benefits, solid-state image-sensing devices employing a buried photodiode PDa have been attracting much attention as low-noise, high-sensitivity solid-state image-sensing devices.
Moreover, in the pixel configured as shown in FIG. 17, by setting at an intermediate voltage the gate voltage at the gate electrode 23, which determines the potential state of the transfer gate TG, it is possible to switch the operation of the pixel between linear conversion operation, which yields an electric signal that varies linearly with respect to the amount of incident light, and logarithmic conversion operation, which yields an electric signal that varies logarithmically with respect to the amount of incident light. Moreover, by making the MOS transistors T11 and T12 operate simultaneously in all pixels, it is possible to hold a potential commensurate with the amount of incident light in the N-type floating diffusion layer FD simultaneously in all pixels. Thus, also with a solid-state image-sensing device of which each pixel is configured as shown in FIG. 16, image sensing operation in global shutter mode can be achieved.
A solid-state image-sensing device of which each pixel is typically configured as shown in FIG. 15 requires, compared with the configuration shown in FIG. 14, two more MOS transistors and one more capacitor. This not only increases the size per pixel but also narrows the area that can be secured for the photodiode PD, imposing limits on aperture ratio improvement and pixel size reduction. Moreover, since electric charge is transferred between the capacitors C and C1, only half of the electric charge is transferred to the capacitor C1. This reduces the amount of electric charge sampled in the capacitor C1. Furthermore, since the transfer of electric charge between the capacitors C and C1 is performed by the MOS transistor T100, noise ascribable to MOS transistor T100 may be added to the resulting signal.
On the other hand, in a solid-state image-sensing device of which each pixel is typically configured as shown in FIG. 16, so long as linear conversion operation is performed to output an image signal, the photoelectric charge generated in the photodiode PD by incident light is accumulated and, even without an integrating circuit, an integrated image signal is outputted. By contrast, when logarithmic conversion operation is performed to output an image signal, irrespective of variation in the amount of incident light during the exposure period, an image signal is outputted with the value at the moment that the MOS transistor T11 is turned off. Thus the pixel configured as shown in FIG. 16 outputs an integrated, linearly converted image signal or an unintegrated, logarithmically converted image signal. As a result, compared with the signal obtained by linear conversion operation, during which an integrated component is available, the signal obtained by logarithmic conversion operation contains large variation and is susceptible to noise.
Thus, disadvantageously, in a case where the amount of incident light is likely to vary, as in long-exposure or flash-light shooting, and in addition a logarithmically converted image signal is outputted, as when the brightness of the subject is high, it is impossible to obtain subject information accurately. Moreover, when such a logarithmically converted image signal is outputted, as the brightness of illumination light varies, flickering occurs.